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INTEGRATED CIRCUITS
74LVC109 Dual JK flip-flop with set and reset; positive-edge trigger
Product specification Supersedes data of 1997 Mar 18 IC24 Data Handbook 1998 Apr 28
Philips Semiconductors
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset; positive-edge trigger
74LVC109
FEATURES
* Wide supply voltage range of 1.2 to 3.6 V * In accordance with JEDEC standard no. 8-1A. * Inputs accept voltages up to 5.5 V * CMOS low power consumption * Direct interface with TTL levels * Output capability: standard * ICC category: flip-flops
DESCRIPTION
The 74LVC109 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT109. The 74LVC109 is a dual positive-edge triggered JK-type flip-flop featuring individual J, K inputs, clock (CP) inputs, set (SD) and reset (RD) inputs; also complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. The J and K inputs control the state changes of the flip-flops as described in the mode select function table. The J and K inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. The JK design allows operation as a D-type flip-flop by tying the J and K inputs together. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25C; tr = tf 2.5 ns SYMBOL tPHL/tPLH fmax CI CPD PARAMETER Propagation delay nCP to nQ, nQ nSD to nQ, nQ nRD to nQ, nQ Maximum clock frequency Input capacitance Power dissipation capacitance per flip-flop VI = GND to VCC1 CONDITIONS TYPICAL 4.0 4.5 4.5 250 5.0 27 UNIT ns MHz pF pF
CL = 50 pF; VCC = 3.3 V
NOTE: 1. CPD is used to determine the dynamic power dissipation (PD in W) PD = CPD x VCC2 x fi ) (CL x VCC2 x fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL x VCC2 x fo) = sum of the outputs.
ORDERING INFORMATION
PACKAGES 16-Pin Plastic SO 16-Pin Plastic SSOP Type II 16-Pin Plastic TSSOP Type I TEMPERATURE RANGE -40C to +85C -40C to +85C -40C to +85C OUTSIDE NORTH AMERICA 74LVC109 D 74LVC109 DB 74LVC109 PW NORTH AMERICA 74LVC109 D 74LVC109 DB 74LVC109PW DH PKG. DWG. # SOT109-1 SOT338-1 SOT403-1
PIN CONFIGURATION
1R D 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 V CC 2R 2J 2K 2CP 2S D D
PIN DESCRIPTION
PIN NUMBER 1, 15 2, 14, 3, 13 4, 12 5, 11 6, 10 7, 9 8 16 SYMBOL 1RD, 2RD 1J, 2J, 1K, 2K 1CP, 2CP 1SD, 2SD 1Q, 2Q 1Q, 2Q GND VCC FUNCTION Asynchronous reset input (active LOW) Synchronous inputs; flip-flops 1 and 2 Clock input (LOW-to-HIGH, edge-triggered) Asynchronous set inputs (active LOW) True flip-flop outputs Complement flip-flop outputs Ground (O V) Positive supply voltage
1J 1K 1CP 1S D 1Q 1Q GND
2Q 2Q
SV00517
1998 Apr 28
2
853-1947 19308
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset; positive-edge trigger
74LVC109
LOGIC SYMBOL (IEEE/IEC)
5 S 2 1J 4 C1 3 1K 1 R 15 R 7 13 1K 12 C1 9 6 14 1J 11 S 10
FUNCTIONAL DIAGRAM
5 1SD 1J SD J Q FF1 Q RD 1 1RD 11 2SD SD (b) 14 2J J Q FF2 Q RD 2Q 9 2Q 10 1Q 7 1Q 6
2
4 1CP CP 3 1K K
(a)
SV00519
12 2CP
CP
LOGIC SYMBOL
5 11 1S D 2S D
13 2K K
15 2RD
SV00520
2 1J 14 2J 4 1CP 12 2CP 3 1K 13 2K
J Q
1Q 6 2Q 10
CP 1Q 7 K Q 2Q 9
1R D 2R D 1 15
SV00518
LOGIC DIAGRAM
K C C C C Q
Q J C S C C C
R C C
CP
SV00521
1998 Apr 28
3
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset; positive-edge trigger
74LVC109
FUNCTION TABLE
INPUTS OPERATING MODES Asynchronous set Asynchronous reset Undetermined Toggle Load "0" (reset) Load "1" (set) Hold "no change" nSD L H L H H H H nRD H L L H H H H nCP X X X nJ X X X h l h l nK X X X l l h h nQ H L H q L H q OUTPUTS nQ L H H q H L q
NOTES: H = HIGH voltage level h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition L = LOW voltage level I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition q = lower case letters indicate the state of the referenced output one set-up time prior to the LOW-to-HIGH CP transition. X = don't care = LOW-to-HIGH CP transition
RECOMMENDED OPERATING CONDITIONS
SYMBOL VCC VI VO Tamb tr, tf PARAMETER DC supply voltage (for max. speed performance) DC supply voltage (for low-voltage applications) DC input voltage range DC output voltage range Operating free-air temperature range Input rise and fall times VCC = 1.2 to 2.7V VCC = 2.7 to 3.6V CONDITIONS LIMITS MIN 2.7 1.2 0 0 -40 0 0 MAX 3.6 3.6 5.5 VCC +85 20 10 UNIT V V V C ns/V
ABSOLUTE MAXIMUM RATINGS1
In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0V). SYMBOL VCC IIK VI IOK VO IO IGND, ICC Tstg PTOT PARAMETER DC supply voltage DC input diode current DC input voltage DC output diode current DC output voltage DC output source or sink current DC VCC or GND current Storage temperature range Power dissipation per package - plastic mini-pack (SO) - plastic shrink mini-pack (SSOP and TSSOP) above +70C derate linearly with 8 mW/K above +60C derate linearly with 5.5 mW/K VI t 0 Note 2 VO uVCC or VO t 0 Note 2 VO = 0 to VCC CONDITIONS RATING -0.5 to +6.5 -50 -0.5 to +5.5 "50 -0.5 to VCC +0.5 "50 "100 -65 to +150 500 500 UNIT V mA V mA V mA mA C
mW
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1998 Apr 28
4
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset; positive-edge trigger
74LVC109
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions. Voltages are referenced to GND (ground = 0V). LIMITS SYMBOL PARAMETER TEST CONDITIONS Temp = -40C to +85C MIN VIH HIGH level Input voltage VCC = 1.2V VCC = 2.7 to 3.6V VCC = 1.2V VCC = 2.7 to 3.6V VCC = 2.7V; VI = VIH or VIL; IO = -12mA VO OH HIGH level output voltage VCC = 3.0V; VI = VIH or VIL; IO = -100A VCC = 3.0V; VI = VIH or VIL; IO = -12mA VCC = 3.0V; VI = VIH or VIL; IO = -24mA VCC = 2.7V; VI = VIH or VIL; IO = 12mA VOL LOW level output voltage VCC = 3.0V; VI = VIH or VIL; IO = 100A VCC = 3.0V; VI = VIH or VIL; IO = 24mA II ICC ICC Input leakage current Quiescent supply current Additional quiescent supply current per input pin VCC = 3 6V; VI = 5 5V or GND 3.6V; 5.5V VCC = 3.6V; VI = VCC or GND; IO = 0 VCC = 2.7V to 3.6V; VI = VCC -0.6V; IO = 0 "0 1 "0.1 0.1 5 GND VCC*0.5 VCC*0.2 VCC*0.6 VCC*1.0 0.40 0.20 0.55 "5 10 500 A A A V VCC V VCC 2.0 GND 0.8 V TYP1 MAX V UNIT
VIL
LOW level Input voltage
NOTE: 1. All typical values are at VCC = 3.3V and Tamb = 25C.
AC CHARACTERISTICS
GND = 0 V; tr = tf v 2.5 ns; CL = 50 pF; RL = 500W; Tamb = -40_C to +85_C LIMITS SYMBOL PARAMETER WAVEFORM VCC = 3.3V 0.3V MIN tPHL/tPLH tPLH Propagation delay nCP to nQ, nQ Propagation delay nSD to nQ nRD to nQ Propagation delay nSD to nQ nRD to nQ Clock pulse width HIGH or LOW Set or reset pulse width HIGH or LOW Removal time nSD, nRD to nCP Set-up time nJ, nK to CP Hold time nJ, nK to nCP Maximum clock pulse frequency Figures 1, 3 Figures 2, 3 TYP1 4.3 4.5 MAX 7.5 8.0 MIN VCC = 2.7V TYP
NO TAG
UNIT MAX 8.5 9.0 ns ns
tPHL tW tW trem tsu th fmax
Figures 2, 3 Figure 1 Figure 2 Figure 2 Figure 1 Figure 1 Figure 1 3.3 3.0 3.0 2.5 2.0 150
5.2 2.0
9.0
10
ns ns ns ns ns ns
225
MHz
NOTE: 1. These typical values are at VCC = 3.3V and Tamb = 25C.
1998 Apr 28
5
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset; positive-edge trigger
74LVC109
AC WAVEFORMS
VM = 1.5 V at VCC 2.7 V; VM = 0.5 x VCC at VCC < 2.7 V. VOL and VOH are the typical output voltage drop that occur with the output load.
VI nJ, nK INPUT GND Vl VM t su t su 1/f max nCP INPUT GND th Vl nSD INPUT GND Vl t PLH nRD INPUT GND VM VOH nQ OUTPUT VOL VM VOH nQ OUTPUT VOL VM VM tPHL tPLH tPLH VM tPHL VM tW tW t PHL VOH nQ OUTPUT VOL VOH nQ OUTPUT VOL t PLH t PHL trem tW trem VM
th
VI nCP INPUT GND
VM
The shaded areas indicate when the input is permitted to change for predictable output performance.
SV00522
SV00523
Figure 1. Clock (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the nJ and nK to nCP set-up, the nCP to nJ, nK hold times and the maximum clock pulse frequency.
Figure 2. Set (nSD) and reset (nRD) input to output (nQ, nQ) propagation delays, the set and reset pulse widths and the nRD, nSD to nCP removal time.
TEST CIRCUIT
tW 90% VM 10% tTHL (tf) tTLH (tr) CL RL POSITIVE PULSE 10% 90% VM tW 90% VM 10% 0V 10% 0V tTLH (tr) tTHL (tf) VI VM VI
Vcc
S1
2 < VCC
Open GND
90% NEGATIVE PULSE
Vl PULSE GENERATOR RT D.U.T.
VO
RL
Test Circuit for Outputs
VM = 1.5V Input Pulse Definition
SWITCH POSITION
TEST tPLH/tPHL S1 Open VCC < 2.7V 2.7-3.6V 4.5 V VI VCC 2.7V VCC
DEFINITIONS
RL = Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance: See AC CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators.
SV00904
Figure 3. Load circuitry for switching times.
1998 Apr 28
6
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset; positive-edge trigger
74LVC109
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
1998 Apr 28
7
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset; positive-edge trigger
74LVC109
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm
SOT338-1
1998 Apr 28
8
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset; positive-edge trigger
74LVC109
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
1998 Apr 28
9
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset; positive-edge trigger
74LVC109
DEFINITIONS
Data Sheet Identification
Objective Specification
Product Status
Formative or in Design
Definition
This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product.
Preliminary Specification
Preproduction Product
Product Specification
Full Production
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 05-96 9397-750-04489
Philips Semiconductors
1997 Mar 18 10

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